This disclosure relates to storing data in a non-volatile memory based on data access frequency, and more specifically, to storing data in a non-volatile memory in bandwidth optimized or coding rate optimized code words based on data access frequency.
Flash memory (or simply flash) is a non-volatile memory technology that stores one or more bits of data per memory cell as a charge on a floating gate of a transistor. As cell densities and the number of bits stored per cell in flash continue to increase in subsequent generations of flash technology, the data stored in the memory cells become more vulnerable to bit errors induced by read disturbs, high ambient temperatures, long storage durations, and other factors. Consequently, the number of read/write cycles for which flash memory devices are rated has generally been declining even while storage density and cost per unit of data have been improving.
In digital transmission and storage, data may be detected as including errors and data may be corrected or discarded. The likelihood that a particular bit is detected as being erroneous, prior to performing any error correction, is known as the raw bit error rate (RBER). Uncorrected bit error rate (UBER) is another quality metric in digital transmission and storage. UBER characterizes the likelihood that a given bit is erroneous following the performance of any error correction. Error-correcting codes (ECCs) modify stored or transmitted data (generally by adding redundant information to the original data) so that errors may be corrected after receipt or retrieval of the data. ECC memory may be used in, for example, data processing systems where data corruption cannot generally be tolerated (e.g., scientific or financial computing). For example, a flash memory controller may implement an ECC and may be employed in a solid-state drive (SSD), e.g., a flash drive, that is used in place of a hard disk drive (HDD).
Due to the design of flash, data of a flash memory device cannot be directly overwritten (as contrasted with data on an HDD which can be directly overwritten). When data is first written to a flash, memory cells of the flash all start in an erased state and data is usually written to the memory cells in pages (e.g., 16 kilobyte (kB) pages). In general, a flash controller of the flash drive manages the flash and interfaces with the host system using a logical-to-physical mapping system (commonly known as logical block addressing (LBA)) provided by a flash translation layer (FTL). When new data is received by the flash controller to replace older data already written to the memory cells, the flash controller writes the new data to a new physical location and updates the logical mapping to point to the new physical location. In this case, the data in the old physical location is no longer valid and needs to be erased before data can be written to the old physical location again. As is known, flash can only be programmed and erased a limited number of times (often referred to as the maximum number of program/erase (P/E) cycles) over the life of the flash. In general, single-level cell (SLC) flash is designed for higher performance and longer endurance and can typically operate between 50,000 and 100,000 cycles. In contrast to SLC flash, multi-level cell (MLC) flash is designed for lower cost applications and has a reduced P/E cycle count (i.e., the P/E cycle count for MLC flash is typically between 3,000 and 5,000 P/E cycles).
As is known, write amplification (WA) is an undesirable phenomenon associated with non-volatile memory (e.g., flash) where the actual amount of physical information written is a multiple of the logical amount intended to be written. Because flash is designed to be erased before the flash can be rewritten, the process to perform write operations results in moving (or rewriting) user data and metadata more than once. The multiplying effect increases the number of writes required over the life of the flash which shortens the time the flash can reliably operate. The increased writes also consume bandwidth to the flash which may reduce random write performance to the flash. In general, lower WA for a flash is desirable as a lower WA corresponds to a reduced number of P/E cycles to write data to the flash and, as such, increased flash drive life.